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C6880-X Datasheet
Original price was: $84,490.00.$46,000.00Current price is: $46,000.00.
| Model: | Cisco Catalyst Switch C6880-X Datasheet Chassis with fixed configuration |
| Detail: | Cisco Catalyst 6800 switch chassis, 5RU, Super 2TXL Engine, no PS, no Fan Tray |
PDF Attachment: C6880-X Datasheet
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- Description
Description
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C6880-X Datasheet Specification |
|
|
QoS Features and Scalability |
|
| Feature | C6880-X Datasheet |
| Layer-3 classification and marking access control entries (ACEs) | 256K shared for QoS/Security |
| Aggregate traffic rate-limiting policers | 16,348 |
| Flow-based rate-limiting method; number of rates | Per source address, destination address, or full flow; 64 rates |
| Layer 2 rate limiters | 20 ingress/6 egress |
| MAC ACLs featuring per-port/per VLAN granularity | Yes |
| Distributed policers | Yes |
| Shared uFlow policers | Yes |
| Egress uFlow policers | Yes |
| Packet or byte policers | Yes |
| Per port per VLAN | Yes |
| COS and DSCP based Queue mapping | Yes |
| Deficit Weighted Round Robin Scheduler (DWRR) and Weighted Random Early Detection Scheduler (WRED) | Yes |
| Receive and Transmit Queues | Default: 1p7q4t
Configurable: 2p6q4t |
|
Security Features and Scalability |
|
| Port security | Yes |
| IEEE 802.1x and 802.1x extensions | Yes |
| VLAN and router ACLs and port ACLs | Yes |
| 1:1 mask ratio to ACE values | Yes |
| Security ACL entries | 256K shared for QoS/Security |
| CPU rate limiters (DoS protection) | 57 |
| uRPF check (IPv4/IPv6) | Up to 16 |
| Number of interfaces with unique ACL | 16k |
| RPF interfaces | 16 |
| Private VLANs | Yes |
| MAC ACLs on IP | Yes |
| Layer 2 and Layer 3 Cisco TrustSec
(Security Group Tagging & Security Group Access Control List) |
Yes |
| IEEE 802.1ae (MACsec) Layer 2 encryption in hardware | Yes |
| CPU HW rate limiters by PPS or BPS | Yes |
| CoPP for multicast | L2 and L3 support |
| CoPP for exceptions (MTU, TTL) | Yes |
| CoPP exceptions NetFlow support | Yes |
| ACL labels | 16K |
| Port ACL | 8K |
| ACL dry run | Yes |
| Hitless ACL changes | Yes |
|
MPLS and Virtualization Features |
|
| VSS* | Yes |
| Label imposition/disposition (MPLS-PE), swapping (MPLS‑P) | Yes |
| Label Distribution Protocol (LDP) | Yes |
| MPLS VPN | Yes |
| VRF Lite | Yes |
| EVN | Yes |
| QoS mechanisms using experimental (EXP) bits | Yes |
| MPLS-RSVP-TE | Yes |
| MPLS differentiated services (diffserv)-aware traffic engineering (MPLS-DS-TE) | Yes |
| MPLS traceroute | Yes |
| EoMPLS | Yes |
| EoMPLS tunnels | 16k |
| IPv4 and IPv6 in IPv6 tunneling | Yes |
| IPv6 in IPv4 tunnelling (Intra-Site Automatic Tunnel Addressing Protocol [ISATAP], 6to4, GRE | Yes |
| QoS support for uniform, short pipe and pipe mode tunnel | Yes |
| Native VPLS in HW | Yes |
| Native L2 over multipoint GRE | Yes |
| VRF-aware operational contexts | Yes |
| VPN NetFlow support | Yes |
| VPN aware NAT | Yes |
| VRF-lite scalability | VLAN reuse per subinterface |
| Per VPN interface statistics | Yes |
|
Netflow and Multicast Features |
|
| Netflow support in hardware | Yes |
| Flexible Netflow | Yes |
| Sampled Netflow | Yes |
| Ingress/Egress Netflow | Yes |
| Ingress and Egress replication in hardware | Yes |
| IGMPv3 snooping in hardware | Yes |
| IPv6 MLDv2 snooping in hardware | Yes |
| PIM registers in hardware | Yes |
| Label Switched Multicast (LSM) | Yes |
|
Base System Scalability |
|
| MAC entries | 128K |
| Routes | 2048K (IPv4)
1024K (IPv6) |
| ACL entries | 256K shared for QoS/Security |
| NetFlow entries | 1024K (per module slot)
Up to 5M per system |
| Multicast routes | 128K (IPv4)
128K (IPv6) |
| IPv4 routing | In hardware
Up to 300 Mpps** |
| IPv6 routing | In hardware
Up to 150 Mpps** |
| L2 bridging | In hardware
Up to 300 Mpps** |
| Jumbo frame support | Up to 9216 bytes
(For bridged and routed pkts.) |
| VLAN | 4K |
| Bridge domains | 16K |
| MPLS | In hardware (up to 8192 VRFs at 300 Mpps**) |
| Logical interfaces | 128K |
| EtherChannel hash | 8 bits |
| VPLS | In hardware (up to 150 Mpps**) |
| GRE | In hardware (up to 150 Mpps**) |
| NAT | Hardware assisted |
| Onboard memory | 4GB |
| Ingress buffers | 1.25MB per 10G port in 2:1 mode
2.5MB per 10G port in 1:1 mode (10MB per Port ASIC) |
| Egress buffers | 24MB per 10G port in 2:1 mode
48MB per 10G port in 1:1 mode (192MB per MUX FPGA) |
|
Software Packaging |
|
| Software License | ● IP Services
● Advanced Enterprise Services |
| Software compatibility | 15.1(2)SY1 and later releases* |
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